Researchers from the Oregon State University College of Engineering have created a more energy-efficient chip designed to counteract the significant power consumption associated with big-language-model AI applications such as Gemini and GPT-4.
“We’ve created a novel chip that uses only half the power of conventional designs,” stated doctoral candidate Ramin Javadi. Alongside Tejasvi Anand, an associate professor of electrical engineering, he unveiled this technology at the conference.
IEEE Conference on Custom Integrated Circuits
in Boston.
The issue lies in the fact that the energy needed to send one bit isn’t decreasing at the pace that the demand for higher data rates is rising,” stated Anand, who leads the Mixed Signal Circuits and Systems Lab at OSU. “This is responsible for the massive amount of power consumed by data centers.”
The new chip itself is based on AI principles that reduce electricity use for signal processing, Javadi said.
“Large language models need to send and receive tremendous amounts of data over wireline, copper-based communication links in data centers, and that requires significant energy,” he said. “One solution is to develop more efficient wireline communication chips.”
According to Javadi, when data is transmitted at high speeds, it often becomes corrupt upon reception and needs to be corrected. Many traditional wired communication systems employ an equalizer for this purpose; however, these equalizers tend to consume quite a bit of power.
Javadi mentioned that they are employing these AI guidelines directly on the chip to recuperate data in a more intelligent and efficient manner by instructing the on-chip classifier to identify and rectify errors.
Javadi and Anand are working on the next iteration of the chip, which they expect to bring further gains in energy efficiency.
More information:
A transceiver operating at 42Gb/s using PAM-4 with consecutive symbol to center (CSC) encoding and classification, designed to handle up to 26dB loss, achieving an energy efficiency of 0.055pJ/bit/dB, fabricated in a 16nm FinFET process.
Provided by Oregon State University
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